1. Field of the Invention
The present invention relates generally to Phase-Locked Loop (PLL) frequency synthesizers, and more particularly, to PLL frequency synthesizers which operate to decrease the difference between the ideal and the realized output energy of a PLL frequency synthesizer's charge pump circuit, and a method of performing the same.
2. Description of the Related Art
PLL frequency synthesizers are frequently used in mobile communication devices such as portable telephones, cordless telephones, and a variety of other well known applications. A PLL frequency synthesizer generates a comparison signal by frequency-dividing a frequency signal output from a voltage controlled oscillator. Based on the difference between the phase of the comparison signal and the phase of a reference signal, a charge pump circuit outputs a voltage signal. The voltage controlled oscillator outputs a controlled frequency signal in accordance with the voltage signal. The controlled frequency signal from the voltage controlled oscillator is then frequency-divided again, yielding another comparison signal. The PLL frequency synthesizer repeatedly executes this operation to output a frequency signal whose level is locked to some multiplication of the level of the reference signal.
An ideal PLL frequency synthesizer operates such that the output energy of the charge pump circuit is a truly linear function (i.e., linear with no offset) of the phase difference between the reference signal and the output signal. FIG. 8A is a graph of a curve 300 of the ideal PLL frequency synthesizer. The curve 300 plots the output energy along the vertical axis as a function of the phase difference plotted along the horizontal axis.
However, due to delay actually occurring in the charge pump circuit, the realized PLL frequency synthesizer only responds to an absolute phase difference greater than some small, but substantial, amount. As a result, the charge pump circuit has a deadband wherein the output energy is substantially zero regardless of the phase difference, as shown by a curve 305 in FIG. 8B. To prevent the occurrence of such a deadband, the charge pump circuit is generally designed in such a manner that the output energy overlaps near the origin and the phase difference characteristic, although non-linear, no longer has a deadband, as indicated by a two-dot chain line 310 in FIG. 8C.
FIG. 17 shows a conventional PLL frequency synthesizer 200. A reference frequency divider 201 frequency-divides a crystal oscillation signal having a predetermined frequency output from a crystal oscillator (not illustrated) to yield a reference signal fr and outputs the reference signal fr to a phase comparator 203. A comparison frequency divider 202 frequency-divides a frequency signal fv output from a voltage controlled oscillator (VCO) 206 to yield a comparison signal fp and outputs the comparison signal fp to the phase comparator 203.
The phase comparator 203 compares the phase of the reference signal fr with that of the comparison signal fp, and, in response, outputs a first phase difference signal .phi.R and a second phase difference signal .phi.P to a charge pump circuit 204.
As shown in FIG. 18, the charge pump circuit 204 has a pMOS transistor 210 and an nMOS transistor 211 connected in series between a power supply V.sub.CC and a ground GND. The drains of the pMOS transistor 210 and the nMOS transistor 211 are connected to an output terminal 212 of the charge pump circuit 204. Low-Pass Filter (LPF) 205, as shown in FIG. 17, is connected to the output terminal 212.
The first phase difference signal .phi.R is input to the gate of the pMOS transistor 210, and the second phase difference signal .phi.P is input to the gate of the nMOS transistor 211. Based on the voltage potentials of the first and second phase difference signals .phi.R and .phi.P, the pMOS transistor 210 and the nMOS transistor 211 are turned either on or off. Hence, the charge pump circuit 204 outputs an analog voltage signal Do from the output terminal 212 based on the first and second phase difference signals .phi.R and .phi.P.
The LPF 205 smoothes the voltage signal Do from the charge pump circuit 204 to yield a control voltage signal V.sub.T having a high frequency component removed therefrom, and outputs this signal V.sub.T to the VCO 206. The VCO 206 outputs the frequency signal fv according to the voltage of the control voltage signal V.sub.T. This frequency signal fv is fed back to the comparison frequency divider 202. As this operation is repeatedly and continuously executed, the conventional PLL frequency synthesizer 200 will, theoretically, reach a steady-state where the frequency signal fv of the VCO 206 is locked to a set frequency.
As shown in FIG. 18, the phase comparator 203 has six 2-input NAND gates 221 to 223 and 231 to 233, two 3-input NAND gates 224 and 234, a single 4-input NAND gate 237, three inverters 225, 226 and 235 and a delay circuit 238.
The NAND gate 221 receives the reference signal fr and the output signal, S24, of the NAND gate 224. The NAND gate 221 outputs a signal S21 based on both signals fr and S24. The NAND gate 223 receives the output signal, S22, of the NAND gate 222 as well as the signal S21. The NAND gate 223 outputs a signal S23 based on both signals S21 and S22.
The NAND gate 224 receives the output signal, S38, of the delay circuit 238 as well as the signals S21 and S23. The NAND gate 224 outputs a signal S24 based on the three signals S21, S23 and S38. The inverters 225 and 226 are connected in series to the output terminal of the NAND gate 224, and the inverter 226 outputs the first phase difference signal .phi.R which is in phase with the signal S24.
The NAND gate 222 receives the two signals S23 and S38 and outputs a signal S22 based on both signals S23 and S38. The NAND gate 231 receives the output signal, S34, of the NAND gate 234 as well as the comparison signal fp. The NAND gate 231 outputs a signal S31 based on both signals fp and S34. The NAND gate 233 receives the output signal, S32, of the NAND gate 232 as well as the signal S31. The NAND gate 233 outputs a signal S33 based on both signals S31 and S32.
The NAND gate 234 receives the three signals S31, S33 and S38, and outputs a signal S34 based on those three signals. The inverter 235, which is connected to the output terminal of the NAND gate 234, inverts the signal S34 to output the second phase difference signal .phi.P.
The NAND gate 232 receives the two signals S33 and S38, and outputs a signal S32 based on those two signals. The NAND gate 237 receives the four signals S21, S23, S31 and S33, and outputs a signal S37 based on those signals to the delay circuit 238. The delay circuit 238, which comprises even-numbered inverters connected in series, delays the signal S37 and outputs the signal S38 which in phase with the delayed signal S37.
In the thus constituted phase comparator 203, when the reference signal fr goes low, the signal S21 goes high, based on which the signal S24 goes low, causing the first phase difference signal .phi.R to go low, as shown in FIG. 19. Further, when the reference signal fr goes low, the signal S31 goes high. As a result, after the delay time of the NAND gate 234, the signal S34 goes low and the second phase difference signal .phi.P goes high.
When the signals S21 and S31 go high, the signal S37 goes low. Consequently, the signal S38 goes low after a delay time D1 of the delay circuit 238. The transition of the signal S38 to the low level causes both the signals S24 and S34 to go high. As a result, the first phase difference signal .phi.R goes high and the second phase difference signal .phi.P goes low.
In accordance with the phase difference between the reference signal fr and the comparison signal fp and the delay time D1 of the delay circuit 238, the phase comparator 203 outputs the first and second phase difference signals .phi.R and .phi.P. When the two phase difference signals .phi.R and .phi.P are output as overlapped, the output energy of the charge pump circuit 204 has an overlap non-linear area as indicated by the two-dot chain line 310 in FIG. 8C. Because this overlap non-linear area occurs, the desired ideal phase characteristics of the ideal PLL frequency synthesizer cannot be obtained.
Further, it is difficult to mass-produce semiconductor chips equipped with the aforementioned various elements such that they have uniform quality. Therefore, the delay time D1 of the delay circuit 238 varies from semiconductor chip to semiconductor chip even within a single production run. Still further, when the delay time D1 becomes longer to increase the overlap range, the output waveform of the charge pump circuit becomes larger, thus generating spurious noise.